1. Field of the Invention
This invention relates to analog multipliers and, more particularly, to balanced triode analog multipliers for multiplying signals derived from CCD taps.
2. State of the Prior Art
Analog multipliers are used, for example, as weighting elements for charge coupled device (CCD) signal processing applications, such as correlators, convolvers, and transversal filters. This multiplying function can be achieved using an MOS transistor operating in its linear or triode region. A balanced triode multiplier has been used to achieve this goal. In a CCD, a signal is typically tapped from a floating gate which signal is typically a current. However, conductance multiplication using balanced triodes is only effective if the drain input signal is a voltage. Therefore, a buffer has been placed between the floating gate of the CCD and the drain-input to the multiplier. This buffer can be a unity gain inverter.
In order for the balanced triode multiplier to operate linearly (without distortion), the transistors must be operated in the triode region. To effect this goal, the input-drain voltage should be substantially at the same potential as the source terminals of the multiplier. When the transistors in the multiplier and the transistors in the buffer are of the same conductivity type, and the DC potentials derived from the CCD stages are substantially the same, biasing the multiplier into the triode region is difficult because the DC levels derived from the CCD stages cannot provide potentials appropriate to operate the multiplier in the triode region. The result is that the multiplier is linear for only a small range of drain-input voltages. CCD stages with different tap potentials can be used. However, this alternative is inconvenient and impractical.
It is desired that an MOS conductance multiplier be provided that has linear multiplying characteristics for a wide range of drain-input voltages.